Headquartered in Lowell, Massachusetts, MACOM is certified to the ISO9001 international quality standard and ISO14001 environmental management standard.
MACOM has multiple design centers, Si, GaAs and InP fabrication, manufacturing, assembly and test, and operational facilities throughout North America, Europe, Asia and Australia.
In addition, MACOM offers foundry services that represents a key core competency within our business. The foundry provides access to, and control of our broad range of proprietary technologies in an asset light, cost effective structure.
MACOM sells and distributes products globally via a sales channel comprised of a direct field sales force, authorized sales representatives and leading industry distributors.
Our sales team is trained across all of our products to give our customers insights into our entire portfolio.
Our global organization of skilled engineers is driven every day to solve the world’s most demanding wireless and wireline application challenges.
We’re proud of our more than sixty years’ of hands-on experience designing and building analog semiconductor technology across the RF to Light spectrum.
This role is being sourced, to be filled over the next 3 to 6 months.
Senior Analog / RF IC Layout Design Engineer
Job Description :
Layout of market-leading RFIC and Millimetre wave components and subsystems in silicon technology.
Main Duties and Responsibilities :
Take responsibility and ownership for the full silicon layout lifecycle including scheduling, floorplanning, verification and tapeout.
Take responsibility for Foundry interactions.
Supervision of Contractors both on site and off site.
Key Competencies Required :
Experience in use of Cadence 6
High level proficiency in interpretation of CALIBRE / ASSURA / PVS LVS, DRC, ERC
Extensive experience in full-custom IC Layout, specialising in Analog, Mixed-Signal, & RF IC projects
Experience in layout of following blocks is desirable :
LNAs, mixer, pre mixer, buffer stages, VCO, PLLs, DACs, active filters, phase shifters.
Expertise in standard layout practices such as layout matching, parasitics, noise & noise isolation, supply considerations, latch-
up, shielding substrates & wells.
Experience with advanced Silicon technologies, such as SOI, SiGe and RF CMOS
Experience with ESD structures
Experience in layout of lumped and distributed passive structures suchas coplanar waveguides, directional couplers, dividers / combiners, coupled lines, baluns, inductors and capacitors
Must understand quard rings, DNW, PN junctions
Experience with all aspects of chip finishing including top level checks andreticle planning
Excellent planning and organisational skills.
Good interpersonal and communications skills.
Ability to work well in a global team environment
Ability to work independently
Ability to work with the design team to minimize layout re-work by improving processes, checklists, documentation
Scripting skills in PERL or SKILL considered an advantage
PCELL creation experience considered an advantage
Job Qualifications :
A minimum of 10 years relevant experience, with 3+ years in mmWave SiGe or CMOS layout experience